1. Field of the Invention
The present invention relates to receivers, receiving methods, filter circuits, and control methods, and in particular, relates to a receiver in which circuitry with a simple structure, a small size, and low power consumption can be realized while required specifications of a plurality of radio communication systems are being met, a receiving method of the receiver, a filter circuit in which circuitry with a simple structure, a small size, and low power consumption can be realized while required specifications of a plurality of radio communication systems are being met, and a method of controlling the filter circuit.
2. Description of the Related Art
Trends toward finer pattern designing of semiconductor devices are advancing. For digital circuits, lower power consumption and higher speed operations can be performed with the advance. The footprints of digital circuits are also decreasing.
On the other hand, for analog circuits, a decrease in footprints, similar to that in digital circuits, is not expected. In addition, deterioration in characteristics caused by, for example, a reduction in power supply voltage and mismatch between transistors is inevitable.
In consideration of the above-described circumstances, shifting functions realized by analog circuits into a digital domain to reduce analog signal processing components is required for receivers.
The main functions in an analog domain of a receiver in radio communication include, for example, frequency conversion, orthogonal demodulation, channel selection, and automatic gain control (AGC). Efficiently shifting those functions to those in the digital domain needs an analog-to-digital (AD) converter having a high operating frequency and a wide dynamic range.
According to an approach to efficiently meeting the above-described requirements, a direct conversion method using low-pass sigma-delta (ΣΔ) modulation is proposed. This method is disclosed in Ville Eerola, et al., “Direct Conversion Using Lowpass Sigma-Delta Modulation”, ISCAS '92, pp. 2653-2656 (Non-patent Document 1).
FIG. 1 shows a related-art circuit disclosed in Non-patent Document 1.
A band pass filter (BPF) 1 limits the frequency band of an input signal S(t) supplied from an antenna (not shown) and then supplies the resultant signal to sigma-delta (ΣΔ) analog-to-digital converters (ADCs) 2I and 2Q.
The ΣΔ ADC 2I operates in accordance with a first clock having a first frequency the same as the carrier frequency of the input signal S(t). The ΣΔ ADC 2Q operates in accordance with a second clock that is π/2 out of phase with the first clock supplied to the ΣΔ ADC 2I. In each of the ΣΔ ADC 2I and 2Q, the signal supplied from the BPF 1 is converted into a single-bit string that is a digital signal and the resultant signal is output.
The output signal of the ΣΔ ADC 2I is supplied to a low pass filter (LPF) and decimator block 3I and is subjected to filtering and decimation, in which the sampling rate is reduced at a predetermined rate. The resultant signal is output as an I-channel (I-CH) signal to a circuit at a subsequent stage.
Similarly, the output signal of the ΣΔ ADC 2Q is supplied to an LPF and decimator block 3Q and is subjected to filtering and decimation. The resultant signal is output as a Q-channel (Q-CH) signal to a circuit at a subsequent stage.
Advantages of this architecture are as follows:
(a) Since sampling is performed using the two clocks, i.e., the first clock having the first frequency the same as the carrier frequency and the second clock which is π/2 out of phase with the first clock, a function for orthogonal demodulation can be realized.
(b) Since the over sampling ratio (OSR) of a signal sampled using the frequency the same as the carrier frequency is high, a wide dynamic range can be realized using the ΣΔ ADCs advantageously having a simple structure. Generally, the carrier frequency is much higher than the signal band. Therefore, when sampling is performed at the same frequency as the carrier frequency, the OSR is high.
(c) Since the analog-to-digital (AD) converters having a wide dynamic range can be realized, functions for channel selection and AGC can be realized as digital domain functions.
However, the above-described architecture is not efficient in terms of power consumption. In the direct conversion method disclosed in Non-patent Document 1, the ΣΔ ADC is allowed to operate in accordance with the same frequency as the carrier frequency, so that the high OSR is ensured. In applications, such as Global System for Mobile Communications (GSM) and Bluetooth (trademark), using narrowband signals, the high OSR is not necessarily needed.
In terms of power consumption, operating each ΣΔ ADC at a more favorable operating frequency obtained by reducing a sampling rate for input signals to obtain a minimum OSR necessary for an application is more efficient than ensuring the high OSR.
A method of sampling input signals at a frequency substantially the same as the carrier frequency of the input signals and reducing the rate of the sampled signals to such a level that the signals can be used at the operating frequency of each ΣΔ ADC using a finite impulse response (FIR) filter or an infinite impulse response (IIR) filter is disclosed in K. Muhammad, et al., “A Discrete-Time Bluetooth Receiver in a 0.13 um Digital CMOS Process”, ISSCC 2004, pp. 268-269 (Non-patent Document 2) and U.S. Patent Application No. 20030080888 (Patent Document 1).
FIG. 2 shows a related-art circuit disclosed in Non-patent Document 2 and Patent Document 1.
A transconductance amplifier 11 converts a voltage input signal supplied from an antenna (not shown) into a current signal and then supplies the signal to a switch 12.
The switch 12 is turned on or off using a frequency the same as the carrier frequency of the input signal. In the ON state, the switch 12 allows a capacitor Ch at a subsequent stage and one of capacitors, indicated by Cr, included in capacitor groups 13 and 14, e.g., a capacitor Cr2 to store charge (hereinafter, also referred to as a charge signal) as shown by an arrow A1 in FIG. 2.
Referring to FIG. 2, the capacitor group 13 includes capacitors Cr1 to Cr4 and switches S1 to S8. An output of the switch 12 is connected to the switches S1, S3, S5, and S7 of the switches S1 to S8. To store charge output from the switch 12 to the capacitor Cr1, the switch S1 is connected to a terminal T1. To store charge to the capacitor Cr2, the switch S3 is connected to a terminal T3. To store charge to the capacitor Cr2, the switch S5 is connected to a terminal T5. To store charge to the capacitor Cr4, the switch S7 is connected to a terminal T7.
Among the switches S1 to S8, the switch S2 is connected to a terminal T2 when the charge stored in the capacitor Cr1 is output to a subsequent stage. The switch S4 is connected to a terminal T4 when the charge stored in the capacitor Cr2 is output to the subsequent stage. The switch S6 is connected to a terminal T6 when the charge stored in the capacitor Cr3 is output to the subsequent stage. The switch S8 is connected to a terminal T8 when the charge stored in the capacitor Cr4 is output to the subsequent stage.
The capacitor group 14 includes capacitors Cr5 to Cr8, which operate in a manner similar to those Cr1 to Cr4 in the capacitor group 13, and switches S11 to S18, which operate in a manner similar to those S1 to S8 in the capacitor group 13.
In the capacitor groups having the above-described structure, the respective capacitors Cr each store charge (charge signals) of eight samples and simultaneously output the charge to the subsequent stage, thus realizing functions of a SINC filter and a ⅛ decimator.
For example, when the capacitor Cr1 stores charge of eight samples, a switching operation is performed so that the capacitor Cr1 is turned off and the capacitor Cr2 stores charge. At that time, charge stored in the capacitor Ch is also supplied to the capacitor Cr2, thus realizing a function of an infinite impulse response (IIR) filter.
When the capacitor Cr2 stores charge of eight samples, the switching operation is performed so that the capacitor Cr2 is turned off and the capacitor Cr3 stores charge. When the four capacitors Cr in the capacitor group 13 each store the charge of eight samples by repeating the above-described operation, the switches included in the capacitor groups 13 and 14 and a switch 15 are switched so that all of the charge is stored into a capacitor Cb, thus realizing functions of a SINC filter and a ¼ decimator.
The charge stored in the capacitor Cb is supplied to a ΣΔ ADC arranged downstream of the capacitor Cb through a switch 16.
A current signal is supplied from the transconductance amplifier 11 to the switch 12 while the charge stored in the four capacitors Cr in the capacitor group 13 is stored into the capacitor Cb. Accordingly, when the switch 12 is in the ON state, a signal (charge) output from the switch 12 is supplied to the capacitor group 14.
Charge of eight samples is sequentially stored into each of the respective capacitors Cr included in the capacitor group 14 in order from the capacitor Cr5. When the capacitors Cr5 to Cr8, i.e., the four capacitors Cr store the charge, the capacitor group 13 operates in place of the capacitor group 14.
The circuit of FIG. 2 realizes a system shown in FIG. 3 by repeating the above-described operation. FIG. 3 shows the functions realized by the circuit 2 in a system.
In other words, the transconductance amplifier 11 in FIG. 2 is represented as a transconductance amplifier 21 in FIG. 3, the switch 12 in FIG. 2 is represented as a sampler block 22. A circuit portion including the capacitor Ch, the capacitor groups 13 and 14, the switch 15, and the capacitor Cb in FIG. 2 is represented as a SINC filter 23, a decimator block 24, an IIR/SINC filter 25, and a decimator block 26.
The decimator block 24 implements ⅛ decimation corresponding to the number of charge signals stored in one capacitor Cr included in the capacitor groups 13 and 14 in FIG. 2. The decimator block 26 implements ¼ decimation corresponding to the number of capacitors Cr arranged in one capacitor group.